An EEPROM cell varies the charge stored on a floating gate in order to vary the threshold voltage, V.sub.T, of a floating gate-type MOS transistor comprising a source, a drain, the floating gate and a control gate. For present purposes, an EEPROM cell is said to be "erased" when the V.sub.T of the transistor is less than some predetermined switch point voltage, V.sub.TSP. The cell is said to be "programmed" when the V.sub.T of the cell is greater than V.sub.TSP. As is familiar, V.sub.TSP is chosen to be less than the positive supply voltage V.sub.DD in static arrays and is approximately equal to V.sub.DD in dynamic arrays. Making the charge stored on the floating gate more positive decreases the V.sub.T of the transistor and making the charge stored on the floating gate more negative increases the V.sub.T of the transistor. As is familiar, charge is added to or removed from the floating gate by tunneling, channel hot carrier injection, avalanche injection or other techniques.
Nearly every commercially successful EEPROM uses at least two transistors per cell. In addition to the floating gate-type device, a series select transistor is present in each cell to alleviate the problem of read errors caused by over-erasure. Because the erasure process is not self-limiting, it is likely that too much negative charge will be removed from (or positive charge added to) the floating gate when the cell is erased, rendering the V.sub.T of the transistor negative (in other words, making it a depletion-mode device). Without series select transistors used for read access, such depletion-mode devices cause read errors when any other cell on the shared bit-line is accessed.
The required use of select transistors in EEPROM's limits the desired increase in density of such devices. Therefore, attempts have been made to overcome this problem. U.S. Pat. No. 4,451,905 (hereinafter, the '905 patent) discloses an EEPROM cell and array using a single transistor design. The approach of the '905 patent is to add extra decoders and an extra (-5V) power supply outside of the array itself to ensure that read errors are avoided. This saves area in the array itself, but may require just as much added area in the extra decoders and power supply.
U.S. Pat. No. 4,317,272 (hereinafter, the '272 patent) discloses a two transistor EEPROM cell in which the two transistors are, to the greatest extent possible, merged together. This saves a certain amount of area, but is still limited to a two transistor design. U.S. Pat. No. 4,486,769 (hereinafter, the '769 patent) discloses what is apparently a single transistor EEPROM cell design. However, a complex triple poly (three layers of polysilicon) process, an additional bias electrode and four connections to each cell (as opposed to the more conventional three) are required by this design. No mention of a solution to the over-erasure problem is made in the '769 patent.